RISC and CISC Architectures - Difference, Advantages and Disadvantages-Titik Letak-Titik Letak

RISC and CISC Architectures:

Every processor is built with the ability to execute a set of instructions for performing a limited set of basic operations. The instruction set architecture is the part of the processor which is necessary for creating machine level programs to perform any mathematical or logical operations.
The instruction set is embedded in the hardware which serves as a bridge between software and hardware. A compiler translates high level language to machine language.
If number of complex instructions within the instruction set of processor is increased, the processor working is slow down due to more complex decoding of instructions and time consuming.
The important aspect of computer architecture or any other microprocessor device is the design of the instruction set for the processor. This is because all operating systems and software applications are programmed within the boundaries of processor’s instruction set.
So a unique instruction set is employed for each processor, where machine language programs of one processor will not run on different processor.

There are two common types of architectures based on the instruction set, namely CISC (Computer Instruction Set Computer) and RISC (Reduced Instruction Set Computer). Let us discuss these two architectures in brief and their difference.

CISC (Computer Instruction Set Computer) Architecture:

Before the processor executes the instructions, the compiler convert instructions in high level languages into their equivalent low level languages as mentioned above.
If these high level languages are programmed for complex mathematical functions, compilers had to convert or translate complex subroutines into long sequences of machine functions. So the compiler development was time consuming and tricky.
In order to make easy development of the compiler, CISC was developed. The main aim of designing CISC based processors is to build the processor with more complex instruction set.
Writing instructions or programming for a CISC processor is easier as it provides single machine instruction for the statements that are written in a high-level language.
CISC incorporates an instruction with variable length format. The instructions that require register operands may take only two bytes while the instructions that require two memory addresses may take five bytes.
Therefore, CISC has the variable length encoding of instructions and the number of clock cycles required to execute the instructions may be varied.
Many CISC architectures, read the inputs and write their outputs in the memory system instead of a register file. The above figure shows the architecture of CISC with microprogrammed control and cache memory.
This architecture uses unified cache memory for holding both data and instructions. Thus, they share the same path for both instructions and data.
In CISC processor, most instructions are stored in memory and they are executed by microprogram. These have many instruction formats and many addressing modes.
In CISC based processor, control signals for the execution of an instruction are generated by a microprogram execution. This mirco program consists of a sequence of microinstructions.
The microinstructions are executed one by one and in turn necessary control signals for the execution of an instruction are produced in steps. This may significantly slow down the instruction execution.
The major characteristics of CISC architecture are
  • It has a large number of instructions, typically from 100 to 250 instructions.
  • It uses a variety of addressing modes, typically from 12 to 24 modes.
  • Instructions that manipulate the operands in memory.
  • Instruction formats have variable length.

Examples of CISC processor

  1. IBM 370/168
  2. Intel 80486
  3. VAX 11/780

RISC (Reduced Instruction Set Computer) Architecture:

In RISC architecture, the instruction set of the computer is simplified to reduce the execution time. It uses small and highly optimized set of instructions which are generally register to register operations.
The speed of the execution is increased by using smaller number of instructions as compared with single long instruction (in case of CISC architecture). And the optimization of each instruction in the processor is achieved through pipeline technique.
The pipelining technique allows the processor to work on different steps of instruction like fetch, decode and execute instructions at the same time. These cycles (fetch, decode and execute) of one or more instructions are overlapped in this pipeline technique.
Therefore, more number of instructions can be executed in a shorter time. In order to avoid more interactions or to reduce access time, RISC processors are provided with multiple sets of registers with optimized register usage so that frequently accessed operands are remain in high-speed storage.
The figure shown above is the architecture of RISC processor, which uses separate instruction and data caches and their access paths also different. There is one instruction per machine cycle in RISC processor.
A machine cycle is defined as the time taken to fetch two operands from registers, perform ALU operation and store the result in a register. Due to this one cycle instruction, execution of instructions carried at a faster rate compared with microinstructions on CISC processor.
Most RISC processors use hardwired control for the machine instruction and hence no need for microinstructions thereby it is not necessary to access a microprogram control memory during instruction execution as in case of CISC processor. The design of the control unit is also simple due to the limited number of instructions.
The major characteristics of RISC architecture are
  • It has reduced and restricted number of instructions.
  • It uses a lesser number of addressing modes.
  • Instruction format is simple and uniform so that most instructions are executed within one cycle.
  • External memory access time is reduced by a larger number of registers.
  • Only load and store instructions have memory access.
  • Hard-wired control rather than micro programmed.
  • Pipeline architecture.
Examples of RISC processors include alpha, AVR, ARM, PIC, PA-RISC, and power architecture.


It consists of a large set of instructions with variable formats (Typically 16 to 64 bits per instruction)It consists of small set of instructions with fixed format and these instructions are of register based instructions.
It has higher number of addressing modes, typically 12 to 24.It has a limited number of addressing modes, typically 3 to 5.
It supports complex addressing modesIn this complex addressing modes are synthesized in software.
It consists of 8 to 24 general purpose registers with a unified cache for instructions and data (recent designs use split caches).It consists of a large number of general purpose registers, typically 32 to 192 with split data cache for instruction cache.
The processor is controlled using microcoded control memory (modern CISC processor also uses hardwired control.)The processor is controlled by a hardwired control without control memory.
It consists of complex instructions that take multiple cycles to execute.It consists of simple instructions that take single cycle to execute.
Instructions are not pipelined or less pipelinedInstructions are pipelined
Complexity lies in microprogramComplexity lies the compiler

Advantages of CISC Architecture:

  • Microprogramming is easy to implement and much less expensive than hard wiring a control unit.
  • It is easy to add new commands into the chip without changing the structure of the instruction set as the architecture uses general-purpose hardware to carry out commands.
  • This architecture makes the efficient use of main memory since the complexity (or more capability) of instruction allows to use less number of instructions to achieve a given task.
  • The compiler need not be very complicated, as the microprogram instruction sets can be written to match the constructs of high  level languages.

Disadvantages of CISC Architecture:

  • A new or succeeding versions of CISC processors consists early generation processors in their subsets (succeeding version). Therefore, chip hardware and instruction set became complex with each generation of the processor.
  • The overall performance of the machine is reduced due to the different amount of clock time required by different instructions.
  • This architecture necessitates on-chip hardware to be continuously reprogrammed.
  • The complexity of hardware and on-chip software included in CISC design to perform many functions.

Advantages of RISC Architecture:

  • The performance of RISC processors is often two to four times than that of CISC processors because of simplified instruction set.
  • This architecture uses less chip space due to reduced instruction set. This makes to place extra functions like floating point arithmetic units or memory management units on the same chip.
  • The per-chip cost is reduced by this architecture that uses smaller chips consisting of more components on a single silicon wafer.
  • RISC processors can be designed more quickly than CISC processors due to its simple architecture.
  • The execution of instructions in RISC processors is high due to the use of many registers for holding and passing the instructions as compared to CISC processors.

Disadvantages of RISC Architecture:

  • The performance of  a RISC processor depends on the code that is being executed. The processor spends much time waiting for first instruction result before it proceeds with next subsequent instruction, when a compiler makes a poor job of scheduling instruction execution.
  • RISC processors require very fast memory systems to feed various instructions. Typically, a large memory cache is provided on the chip in most RISC based systems.
REFERENCE // Electronics Hub

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